Shared busses + ( Bandwidth Hungry Processors * Multiple Processors ) = Electrical Engineering Problems.

Until very recently, with Intel's new Noconoa cores, Xeon's have been stuck at a 533MHz FSB. That isn't to say that the adventuring overclocker can't push it past that. It is just saying that Intel realized they had a problem of operating at an 800MHz bus (really 200MHz Quad-Pumped, but still fast) with two processors because at those speeds an error is fatal. (Which is why until recently, 800MHz was only for their single processor P4's) It is also much harder to get two chips running on an 800MHz bus because of some electrical issues that I don't throughly understand but know exist. A proof that this issue does exist, Intel supports their 800MHz Xeon processors only for dual configurations. Before that, 533MHz was as fast as their Dual Xeon processors would go. Their processors for 4+ CPU's are all at 400MHz. With how bandwidht hungry we've come to see Intel's processors to be, we know they'd want more bandwidth for more processors. But their product lineup is the opposite of that -- something is preventing them from doing that. And it is these electrical/engineering issues. We know Intel will give the better wafers of silicone to become more expensive processors, and that they don't have any faster FSB DP systems shows that Intel has hit some sort of wall. Maybe in the future that will change a bit, judging from how the new cores operate at higher speeds...

http://developer.intel.com/products/...xeon/index.htm <- Intel's Xeon Processors & Specs


So developing for a single bus can infact be more difficult. Think of it like adding another hard-drive to your IDE channel. That is now becoming obsolete because of the performance issues associated with this, and is why SATA has become so popular. (PATA = Single Bus, SATA = Multiple Busses) The market is generally realizing this change, and AMD's solution is now competing with Intel's big name to become more widely used.